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3Com 3c509

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Ethernet network card line
3Com 3c509B-Combo card (3C509BC), second generation for the ISA 16-bit bus and 10BASE-T, AUI and 10BASE-2.

3Com 3c509 is a line of Ethernet IEEE 802.3 network cards for the ISA, EISA, MCA and PCMCIA computer buses. It was designed by 3Com and put on the market in 1992, followed by the improved version 3c509B in 1994.

Features

The 3Com 3c5x9 family of network controllers has various interface combinations of computer bus including ISA, EISA, MCA, and PCMCIA. For network connection, 10BASE-2, AUI and 10BASE-T are used.

Physical card configurations
Combinations for Etherlink III
Adapter number Bus Network Connector
3C509-TPO ISA 10BASE-T 8P8C
3C509B-TPO ISA 10BASE-T 8P8C
3C509-TP ISA 10BASE-T, AUI 8P8C, DA-15
3C509B-TP ISA 10BASE-T, AUI 8P8C, DA-15
3C509B-TPC ISA 10BASE-T, 10BASE2 8P8C, BNC
3C509-Coax ISA AUI, 10BASE2 DA-15, BNC
3C509B-Coax ISA AUI, 10BASE2 DA-15, BNC
3C509-Combo ISA 10BASE-T, AUI, 10BASE2 8P8C, DA-15, BNC
3C509B-Combo ISA 10BASE-T, AUI, 10BASE2 8P8C, DA-15, BNC
3C579 EISA AUI, 10BASE2 DA-15, BNC
3C579-TP EISA 10BASE-T, AUI 8P8C, DA-15
3C529 MCA AUI, 10BASE2 DA-15, BNC
3C529-TP MCA 10BASE-T, AUI 8P8C, DA-15
3C589-TP PCMCIA 10BASE-T 8P8C
3C589B-TP PCMCIA 10BASE-T 8P8C
3C589-Combo PCMCIA 10BASE-T, 10BASE2 8P8C, BNC
3C589B-Combo PCMCIA 10BASE-T, 10BASE2 8P8C, BNC

B = On ISA and PCMCIA, adapter numbers indicate that these adapters are part of the second generation of the Parallel Tasking EtherLink III technology.

The DIP-28 (U1) EPROM for network booting may be 8, 16, or 32 KB in size. This means EPROMs of type 64, 128, and 256 kbit (2^10) are compatible, like the 27C256.

Boot ROM address is located between 0xC0000 - 0xDE000.

Teardown example, the 3c509B-Combo

The Etherlink III 3C509B-Combo is registered with the FCC ID DF63C509B. The main components on the card are Y1: crystal oscillator 20 MHz, U50: coaxial transceiver interface DP8392, U4: main controller 3Com 9513S (or 9545S etc.), U6: 8 kB 70 ns CMOS static RAM, U1: DIP-28 27C256 style EPROM for boot code, U3: 1024 bit 5V CMOS Serial EEPROM (configuration).

Detailed teardown
  • 3C509B-Combo 1994 ASSY 03-0021-001 REV-A 3C509B-Combo 1994 ASSY 03-0021-001 REV-A
  • 3C509B-Combo 1996 ASSY 03-0021-004 REV-B 3C509B-Combo 1996 ASSY 03-0021-004 REV-B

Label: 

 Etherlink III
(C) 1994 3C509B-C
 ALL RIGHTS RESERVED
 ASSY 03-0021-001 REV-A
 FCC ID: DF63C509B

Barcode: 

 EA=0020AFDCC34C
 SN=6AHDCC34C
 MADE IN U.S.A.

R = Resistor C = Capacitor L = Inductance Q = Transistor CR = Transistor FL = Transformer T = Transformer U = Integrated circuit J = Jumper or connector VR F

FL70: Pulse transformer 

 bel9509 A
 0556-3873-03
 * HIPOTTED

Y1: 20 MHz crystal 

 20.000M
    652DA

U50: 

 P9512BR
 DP8392CN
 Coaxial Transceiver Interface

T50: Pulse transformer, pinout: 2x8 

 VALOR
 ST7033

x00: Pulse transformer 

 VALOR
  PT0018
  CHINA M
  9449 C

U4: Plastic package 33x33 pins 

 Parallel Tasking TM
 3Com
 40-0130-002
 9513S 22050553
 AT&T 40-01302

Another chip with the same function: 

 40-0130-003
 9545S 48324401
 AT&T 40-01303

U6: 8192 x 8-bit 70 ns CMOS static RAM 

 HY 6264A
 LJ-70
 9509B KOREA

Another chip with the same function: 

 CY6264-70OSC (photo)

U1: Boot ROM 

 DIP-28 EPROM
 8, 16, or 32 KB (27/28C256) for boot code.

U3: 256 Bit/1K 5.0V CMOS Serial EEPROM 

 B 52AH
  93C46
  M8

Q41: N-Channel Logic level Power MOSFET 60V, 11A, 107 mĪ© (using ASSY 03-0021-004 due to obscured view) 

 F3055L
 96   45
(H)H

VR41: 3-Terminal 0.5 A Negative Voltage Regulator (-5V) in D2PAK 

 KA79
 M05

ASSY 03-0021-004 REV-B has written on it: U.S. Patents: U.S. patent 5,307,459

Connector for the computer bus: ISA 16-bit

Connections for networking: 10BASE-T (8P8C), AUI (DA-15), 10BASE2 (BNC)

Driver setup

Some of the possible ISA I/O bases are 0x280, 0x300, 0x310, 0x320, 0x330, 0x340, 0x350. And IRQ 5, 7, 9, 10, 11, 12. The driver for OpenBSD, NetBSD and FreeBSD is "ep"; for Linux it is "eth".

Patents

3c509B-C from 1996 specify the use of U.S. patent 5,307,459 with a priority date of 1992-07-28.

The patent describes a method where a data transfer counter triggers a threshold logic that generates an early indication or interrupt signal before the transfer is completed. The adapter also writes timing information into status registers such that a device driver can optimize for any latency.

Uses

See also

References

  1. ^ "EtherLink III Parallel Tasking ISA, EISA, Micro Channel, and PCMCIA, Adapter Drivers Technical Reference, Members of the 3Com EtherLink III family of adapters" (PDF) (published 2011-08-29). August 1994. Retrieved 2016-04-06. (PDF)
  2. "3Com 3C509B-TPO - WikiDevi". 2014-09-12. Retrieved 2016-04-06. (HTML)
  3. "import from mindrot Ā· kirei/flashboot@32e5b6b". GitHub. Retrieved 3 August 2017.
  4. "FreeBSD 4.11-RELEASE #1" (TXT). Berklix.com. 2006-12-17. Retrieved 2017-08-04.
  5. "cpu0: Intel 486DX (486-class)" (TXT). Fml.org. Retrieved 2017-08-04.
  6. "LEAF Linux Embedded Appliance Framework / Mailing Lists". sourceforge.net. Retrieved 3 August 2017.
  7. Threads, Gossamer. "Mailing List Archive: no interrupts to 3c509B". Gossamer-threads.com. Retrieved 3 August 2017.
  8. U.S. patent 5,307,459

External links

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